Description
Apple is hiring an SoC Timing Closure Engineer to own timing closure across the full project cycle for complex, multi-clock and multi-voltage System-on-Chip designs in deep sub-micron technologies. The role develops timing constraints, coverage and critical-path analysis scripts, I/O-interface timing, and full-chip and block-level verification flows, while collaborating with cross-functional teams to resolve timing issues. It requires a master’s degree or foreign equivalent in Electrical and Computer Engineering or a related field, along with experience in digital and analog circuits, computer architecture, FSM design, RTL, and C/C++ or Python. The position is 40 hours per week and offers a base-pay range of $148,987 to $194,700 per year, with medical and dental coverage and other benefits.
