Description
Apple is hiring an ASIC RTL Design Engineer to deliver complex digital IPs for Power Management ICs. The role involves RTL design in SystemVerilog, synthesis, PPA analysis, low-power techniques, simulation and functional verification, CDC and RDC analysis, signoff, scripting, and collaboration with analog, architecture, DFT, ATE, and verification teams. The position is based in Cupertino, California or other unanticipated locations throughout the United States, requires a master’s degree in a relevant engineering field plus specified ASIC design and verification experience, and offers a base-pay range of $150,400 to $225,300 per year.
