Description
The Front-End (FE) RTL Infrastructure - CAD Engineer will develop and maintain infrastructure and work environments for RTL design and verification teams, including gatekeeping infrastructure, soft IP development and release methodologies, Perforce administration, centralized configuration management, and generative AI solutions. The role also manages internal training materials, coordinates vendor training, and supports scalable infrastructure across Apple’s HWTech organization. The position requires a bachelor’s degree and three years of relevant experience, along with Python or Perl programming expertise and knowledge of Verilog and SystemVerilog.
