Description
The ASIC STA Engineer will own timing across the ASIC design flow, from synthesis through sign-off, including timing sign-off, STA and sign-off flow development, full-chip and IP-level timing constraints, and timing closure. The role collaborates with RTL, CAD, and physical design teams, develops and verifies timing constraints, and improves timing analysis to address pessimism and timing fallouts. Candidates need at least five years of experience, ASIC timing closure expertise, at least two years of ASIC timing constraint and closure experience, Primetime STA expertise, knowledge of timing corners and modes, and proficiency with Tcl and Perl; a B.Sc. or M.Sc. in Electrical or Computer Engineering is preferred.
