Formal Verification Engineer at Apple

Department: Hardware

Compensation · Listed in posting

$150,400 – $225,300

Location: Cupertino, California
Type: Other
Level: mid
Posted: Sep 28, 2026

Description

The Formal Verification Engineer will work on Apple Silicon’s security enclave and other system-on-chip design blocks, developing formal micro-architecture specifications, security-focused verification test plans, formal models, verification code, and correct-by-construction methodologies. The role involves proving design properties, finding bugs, collaborating with design teams, and improving formal verification efficiency and productivity.

Required Skills

Formal verification
Security verification
Formal modeling
SVA/PSL
EDA tools
Debugging
VLSI design

Additional Information

Minimum Education: Bachelor's degree
Required Previous Experiences: 3 years of relevant industry experience in silicon validation software engineering or a related field
Preferred Qualifications: Hands-on experience with VLSI, digital logic design, verification techniques, and formal methods
Interest in SoC, CPU, GPU, or cellular design
Knowledge of formal methods or formal verification technologies
Experience interpreting hardware specifications
Experience with SVA or PSL
Experience with EDA formal tools and tool development
Scripting proficiency and debugging skills
Excellent interpersonal skills
Exposure to CPU instruction-set architectures, memory consistency, or cache coherence
Translation Company Name: Apple

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