Description
The Senior Technical Lead will provide hands-on leadership for FPGA IP and simulation-model development, design reviews, validation, debugging, and Quartus Prime integration. The role covers RTL and SystemVerilog/VHDL design, behavioral and cycle-accurate simulation, assertion-based verification, testbench and regression infrastructure, root-cause analysis, automation, and engineering productivity improvements, while mentoring engineers. Applicants need a bachelor’s or master’s degree in electrical or computer engineering and 8–12+ years of experience in FPGA design, IP development, or verification.
