FPGA IP Software Development Engineer at Altera

Location: Bengaluru, Karnataka
Type: Full-time
Level: senior
Posted: Aug 25, 2026

Description

The RTL Design Engineer will own the end-to-end FPGA Soft IP development lifecycle, from micro-architecture and RTL coding through synthesis, place-and-route, timing closure, simulation, hardware bring-up, and validation. The role requires a bachelor’s or master’s degree in a relevant engineering discipline, at least seven years of production-grade RTL experience, FPGA toolchain expertise, static verification and constraint troubleshooting skills, and scripting ability. The position is based in Bengaluru, Karnataka, India, and is a regular full-time role.

Required Skills

RTL coding
System Verilog
Verilog
VHDL
FPGA tool flow
Timing closure
Static timing analysis
Tcl scripting
Python scripting
Shell scripting

Additional Information

Minimum Education: Bachelor’s or master’s degree in Electronics Engineering, Electrical Engineering, VLSI, Embedded Systems, or a closely related technical discipline
Required Previous Experiences: 7+ years of dedicated experience writing production-grade RTL using System Verilog, Verilog, or VHDL
Preferred Qualifications: Familiarity with embedded SoC architectures such as ARM Cortex and RISC-V, and hardware-software co-design
Translation Company Name: 844 Altera Semiconductor Technology India Pvt. Ltd.