The Front-End ASIC Design Engineer will own RTL blocks for high-performance SoCs, translating architectural specifications into synthesizable SystemVerilog/Verilog and driving front-end sign-off through STA, lint, CDC/RDC, synthesis, QoR, and power analysis. The role also includes RTL optimization, formal and assertion-based verification, power estimation, methodology improvement, scripting, and regression automation, with work supporting HPC and AI accelerator silicon.
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