Description
STMicroelectronics is seeking a SoC Timing Constraints Lead to develop and validate digital IP-level and SoC timing constraints, perform static timing analysis and constraint verification, debug timing violations, and collaborate with synthesis, place-and-route, and verification teams to achieve design closure. The role also involves optimizing designs for area, power, and timing, participating in design reviews, contributing to technical documentation, and supporting digital block integration and silicon bring-up.
