Description
The role is responsible for implementing complete GPU chip design from RTL through tapeout, including early physical-design collaboration with the FE team, PPA optimization, technology-node design, place-and-route coordination, flow and design-issue resolution, and supervision of physical-design execution. It requires a bachelor’s degree in engineering or computer science, relevant ASIC implementation coursework or experience, digital-logic and VLSI knowledge, and scripting-language experience; a master’s degree and broader ASIC implementation expertise are preferred.
