Description
The role is responsible for implementing complete GPU chip design from RTL through tapeout, including early physical design, floorplanning, placement and routing, PPA optimization, design-flow leadership, and resolution of physical-design issues. It requires a bachelor’s degree plus three years of relevant experience and experience with floorplanning, routing and placement experiments, static timing, and physical-design verification. Preferred qualifications include ASIC implementation across synthesis, DFT, clock and power distribution, timing, electrical and physical signoff, hierarchical design, IP integration, large GPU design experience, and process-related design issues.
