Description
The GPU Top Level Physical Design engineer will implement complete chip design from netlist through tapeout, collaborate with the FE team on RTL and early physical design, develop physical design methodologies and guidelines, drive place-and-route integration, and supervise cross-functional progress. The role requires a BS plus three years of relevant experience, ASIC integration experience, and expertise in floorplanning, physical design flows, global timing verification, and physical design verification.
