Description
The GPU Top Level Physical Design engineer will implement complete chip design from netlist through tapeout, collaborate with the frontend team on RTL and physical design, develop physical design methodologies and guidelines, and lead place-and-route integration at the top level. The role requires a mix of strategic engineering and hands-on technical work, including ASIC integration, floorplanning, clock and power distribution, global and I/O planning, and physical design verification. The posting specifies a bachelor's degree plus 10 years of relevant experience and lists preferred qualifications involving hierarchical design, IP integration, large subsystems, GPU architecture, and yield and manufacturability.
