Graphics Cache Hierarchy Design Verification Engineer at Apple

The Graphics Cache Hierarchy Verification Engineer will perform pre-silicon RTL verification of graphics memory subsystem units, including caches, memory management units, interconnects, and link interfaces. The role involves developing verification plans, building test environments, generating directed and constrained random tests, debugging simulations, creating functional coverage, and establishing automated verification flows using VHDL or Verilog. Candidates need a computer architecture background, experience with CPU or GPU architecture, unit or cluster-level test environments, complex design bring-up and debugging, SystemVerilog, HDL simulators, and waveform viewers, along with at least a bachelor's degree and two years of experience.