Hardware-Assisted Verification Engineer at Synopsys

Language

Location: Hsinchu
Level: not_specified

Description

Synopsys is seeking a highly experienced Hardware-Assisted Verification (HAV) expert specializing in emulation and FPGA prototyping. The role involves driving product innovations in emulation runtime performance, managing the full product lifecycle, collaborating with internal and external stakeholders, providing technical leadership, and leading root cause analyses to resolve performance bottlenecks. The ideal candidate will contribute to creating robust SoC designs and enhance verification processes for high-quality silicon products.

Required Skills

emulation methodology
RTL verification
software bring up
verification
System on Chip (SoC) design bring-up and validation
bus and memory protocols
OSes booting sequence
architecture of emulation / FPGA prototyping platforms
compilation and runtime flows
debug features
root cause analysis

Additional Information

Required Previous Experiences: 12+ years of experience in emulation methodology, spanning early RTL verification to software bring up.
Preferred Qualifications: Proven expertise in verification, with a focus on System on Chip (SoC) design bring-up and validation. This includes an extended knowledge of most frequent bus and memory protocols, and a good understanding of OSes booting sequence.
Comprehensive knowledge of the architecture of emulation / FPGA prototyping platforms and their eco-systems.
A good understanding of the compilation and runtime flows on these emulation platforms.
Demonstrated experience in using debug features of these emulation platforms, and in conducting root cause analysis for emulation runtime performance issues.
Strong collaborative skills, with a track record of working effectively with cross-functional teams to drive product and customer success.