The Memory PHY team is hiring a Hardware Design Engineer 2 for a 12-month assignment in Boxborough, Massachusetts, with a hybrid arrangement requiring 2–3 onsite days. The role focuses on RTL and firmware development of high-speed LPDDR and DDR interface IPs, including participation in the definition, design, and development phases of industry-leading memory PHYs and interface IP.
Every query opens live roles, salary samples, and market demand — tap a search to run it instantly.
Unlock powerful job search, personalized recommendations, and deep career insights from comprehensive, market-leading data and live market signals.
For job seekers
Upload your résumé, start a Job Search Thread, and let Metaintro rank real openings against your experience — then guide you from search to offer.
Match
Compare live roles against your current evidence.
Position
Turn proof projects into role-specific applications.
Improve
Use market feedback to keep the skill plan current.