Description
Normal is hiring an RTL Design Engineer to design and verify digital logic for its thermodynamic hardware. The role owns synthesizable SystemVerilog RTL from microarchitecture through tapeout, collaborates with architecture, verification, and physical design teams, supports timing closure and DFT, and may contribute to post-silicon bring-up. Candidates should have production RTL experience, coverage closure, at least one tapeout, ASIC or SoC design experience, and strong debugging skills.
