Description
Lattice is seeking an experienced Hardware Integration Design Engineer to collaborate with IP designers and modeling teams to ensure timing model requirements align with FPGA tool specifications. The role involves understanding IP functionality, defining timing arcs and constraints, performing quality checks, addressing issues like missing timing arcs and clock information, generating timing reference models, comparing formats, handling custom design simulations, and constructing proprietary timing models. The ideal candidate will have strong knowledge of FPGA power models, proficiency in schematic generation using Cadence Virtuoso, and working knowledge of System Verilog, synthesis, and static timing analysis. They should also possess specialist knowledge in floor-planning, power estimation, and back-end methodologies, along with experience in Linux scripting and Python. This role emphasizes staying current with technological advancements and leveraging AI tools for accelerated content creation and dataset analysis.
