Description
Baya Systems is hiring a Design Verification Engineer to create test plans and UVM/SystemVerilog testbenches for configurable interconnect IP used across SoC, chiplet, and multi-chiplet systems. The role collaborates with software and design teams on test implementation, failure debugging, coverage, and verification, with a focus on Arm AMBA protocols, modern programming, and IP subsystems. The position is based in Bristol, Cambridge, or London, England, and offers medical, dental, vision, retirement, equity, and performance-incentive benefits.
