Description
Baya Systems is hiring a Design Verification Engineer in Austin, Texas to create test plans and UVM/SystemVerilog testbenches for configurable interconnect IP used across SoC, chiplet, and multi-chiplet systems. The role collaborates with software and design teams on test implementation, failure debugging, and coverage, and requires extensive IP-level verification experience, UVM expertise, and knowledge of Arm AMBA protocols. The position offers salary commensurate with experience, performance incentives, medical, dental, and vision benefits, a 401(k), and equity.
