Description
Micron Technology is hiring a Layout Design Engineering Manager for its High Bandwidth Memory organization in Guadalajara, Mexico. The role leads a distributed team developing analog, mixed-signal, and custom layouts for advanced CMOS technology, oversees LVS, DRC, antenna checks, documentation, and quality reviews, coordinates multiple concurrent projects, and mentors layout engineers. Candidates need 15+ years of analog/custom layout experience, 5+ years managing layout engineering teams, a bachelor’s or master’s degree in a relevant field, and expertise with Cadence VLE/VXL and Mentor Graphics Calibre.
