HPC SoC Interconnect Design Engineer / Leader at RenesasElectronics

Seniority in posting: director

Language

Setup: On-site
Location: Tokyo
Type: Full-time
Level: lead/mgmt
Posted: Sep 4, 2026

Description

Renesas is hiring an SoC Bus/Interconnect Engineer/Leader to develop and lead the design of on-chip buses and NoCs for R-Car automotive SoCs. The role covers AXI and other protocol specifications, RTL design, verification, debugging, performance evaluation, bottleneck analysis, and design improvement, while coordinating with CPU, memory, AI, interface, and IP teams and external IP vendors. The position may work from Japan, India, or Vietnam and requires at least five years of SoC or IP digital circuit design or verification experience, along with English communication skills.

Required Skills

AXI bus
NoC
RTL design
Verification
Debugging
Traffic modeling
Performance evaluation
QoS
Cache coherence
External IP integration

Additional Information

Required Previous Experiences: At least 5 years of SoC or IP development experience in digital circuit design or verification, including RTL design, verification, debugging, specification review, and design review.
Design or verification experience with buses, interconnects, NoCs, or data transfer circuits.
Experience translating design specifications and technical documentation into circuit specifications and verification items.
Experience collaborating with internal and external stakeholders to resolve technical issues through discussion.
Experience organizing design policies and technical issues within an assigned area and reaching agreement with stakeholders.
Ability to read and write technical documents in English or communicate with global teams.
Preferred Qualifications: Knowledge or experience with AMBA AXI, ACE, CHI protocols or NoC architectures.
Experience with QoS, bandwidth control, address mapping, security and access control, error handling, and performance counters.
Experience with traffic analysis, performance models, simulation, performance evaluation, and bottleneck analysis.
Knowledge or experience with cache coherence, memory subsystems, CPU subsystems, and DMA.
Experience leading technical consolidation at the subsystem or IP level.
Experience integrating external IP, organizing constraint conditions, and resolving technical issues with IP vendors.
Knowledge of power separation design and physical design.
Experience developing automotive SoCs or products with high functional-safety, quality, and reliability requirements.
Translation Company Name: Renesas Electronics