Description
The Package Design Engineer will lead the physical design and integration of advanced semiconductor packages across SoC, memory, RF, and cellular technologies, from concept through tape-out. Responsibilities include package substrate layout, parasitic extraction, S-parameter modeling, SI/PI validation, cross-functional feasibility and system co-optimization, and development of automated design and verification flows using AI tools. The role requires a bachelor's degree and at least 10 years of relevant industry experience, with preferred expertise in Cadence Allegro or Mentor Xpedition, high-speed interfaces, SI/PI analysis, manufacturing and DFM, and Python, Perl, or TCL scripting.
