Description
Synopsys is hiring an experienced ASIC Verification Engineer to own verification of complex Interface IP solutions involving PCIe, CXL, DDR, and Ethernet technologies. The role involves developing scalable UVM-based verification environments, defining verification strategies, driving coverage closure and signoff, debugging RTL and protocol issues, and collaborating with architecture, design, firmware, and systems teams. Candidates need a BSEE/MSEE, at least five years of direct industry experience verifying complex ASIC or SoC designs, and deep expertise in SystemVerilog and UVM methodologies.
