Internship - FPGA Hardware Design - PQ Cryptography Hardware Accelerator at CryptoNext Security

CryptoNext Security is hiring an FPGA Hardware Design Engineer for a six-month exploratory internship focused on designing and evaluating hardware accelerators for post-quantum cryptographic functions such as the Number Theoretic Transform and Keccak permutation. The role involves RTL development in SystemVerilog, FPGA integration, hardware/software codesign, and performance evaluation on an AMD Xilinx ZCU104 platform, with the goal of demonstrating acceleration for ML-KEM or ML-DSA implementations in the CryptoNext Quantum Safe Library. The internship is intended for a final-year engineering student or M2/Master's student in a relevant engineering field and runs from December 2026 to June 2027.