Description
Altera is hiring a Senior RTL Design Engineer to lead FPGA architecture and RTL implementation for Altera development kits. The role covers Verilog and SystemVerilog design, Quartus Prime flows, timing closure, board bring-up, interface validation, testbenches, and cross-functional debugging. The position requires a bachelor’s or master’s degree in a relevant engineering discipline and at least 10 years of professional FPGA RTL, implementation, and board bring-up experience. It is a regular full-time role based in Bengaluru, Karnataka, India.
