Summary from listing
Ericsson is hiring a Senior Design Verification Engineer — ASIC IP for its Silicon Verification team in Austin, Texas. The role owns RTL verification across block and top levels, TLM modeling, UVM testbench architecture, hardware emulation and acceleration, and software-driven verification, while also mentoring engineers and helping shape verification methodology. Candidates need several years of industry RTL verification experience, strong SystemVerilog/UVM skills, testbench-building experience, and familiarity with semiconductor technologies such as SerDes, PCIe, ARM subsystems, DSPs, or Ethernet. The position is on-site with a hybrid work schedule and offers medical and dental benefits, a 401(k) match, paid leave, and other company benefits.
