Description
Synopsys is hiring a Senior Layout Engineer in Ho Chi Minh City to design and integrate memory leaf-cell and standard-cell layouts for advanced FinFET technology nodes. The role uses Custom Compiler and physical verification tools such as ICV or Calibre, debugs DRC, LVS, ERC, and antenna violations, collaborates with circuit and verification engineers, and builds Perl, Shell, or TCL automation scripts. Candidates need at least two years of custom, standard-cell, or memory layout experience, familiarity with FinFET design rules, a bachelor's or master's degree in a relevant engineering field, and layout automation experience.
