Description
Synopsys is hiring a Staff Layout Design Engineer in Ho Chi Minh City to design and optimize custom layouts for embedded memory IPs, standard cells, and IO structures. The role uses Cadence Virtuoso, Synopsys Custom Compiler, and Calibre DRC/LVS, focuses on PPA and manufacturability across advanced process nodes, and involves debugging physical design violations, developing layout automation, and collaborating with circuit and verification teams. The position requires a bachelor's or master's degree in a relevant engineering or science field and at least five years of custom IC layout experience.
