Description
Synopsys is hiring a Senior Layout Design Engineer in Da Nang, Vietnam, to design custom memory and standard-cell layouts using Custom Compiler. The role involves translating circuit schematics into physical structures, running and debugging ICV or Calibre physical verification flows, analyzing parasitics and EMIR checks, collaborating with circuit designers, building reusable layout cells, and supporting post-silicon characterization. The position requires a bachelor's or master's degree in electrical or electronics engineering or a related field, at least two years of custom, standard-cell, or memory layout experience, and strong knowledge of MOSFET and FinFET devices, DRC, LVS, ERC, and physical verification tools.
