Description
Synopsys is hiring a Layout Design Sr Engineer in Ho Chi Minh City to design and optimize custom layouts for embedded memory IPs, standard cells, and IO structures. The role uses Cadence Virtuoso, Synopsys Custom Compiler, and Calibre DRC/LVS, and involves optimizing density, performance, power, and manufacturability; debugging physical design violations; developing layout automation; and supporting design reviews and documentation. The position requires a bachelor's or master's degree in a relevant engineering or science field and at least two years of hands-on custom IC layout experience.
