Description
Synopsys is hiring a senior IC layout engineer to design and integrate memory leafcell and standard cell layouts for advanced FinFET technology nodes. The role involves optimizing area, speed, and power; running and debugging DRC, LVS, ERC, and antenna verification flows; collaborating with circuit and verification engineers; and automating layout tasks with Perl, Shell, or TCL. Candidates need at least two years of custom, standard cell, or memory layout experience, familiarity with FinFET design rules and physical verification tools, and a bachelor's or master's degree in a relevant engineering field.
