Synopsys is seeking a senior memory-layout engineering leader to guide physical layout development for SRAM, ROM, eDRAM, and emerging memory types across advanced nodes. The role owns layout architecture, DRC/LVS/ERC/EMIR closure, RC extraction, signal integrity, automation, methodology, and cross-team collaboration with circuit designers and foundry teams, while mentoring senior engineers and shaping memory IP strategies for AI, automotive, HPC, mobile, and cloud applications.
Every query opens live roles, salary samples, and market demand — tap a search to run it instantly.
Unlock powerful job search, personalized recommendations, and deep career insights from comprehensive, market-leading data and live market signals.
For job seekers
Upload your résumé, start a Job Search Thread, and let Metaintro rank real openings against your experience — then guide you from search to offer.
Match
Compare live roles against your current evidence.
Position
Turn proof projects into role-specific applications.
Improve
Use market feedback to keep the skill plan current.
AI Infrastructure
Synopsys delivers comprehensive silicon-to-systems solutions that help innovators accelerate development, reduce risk, and drive breakthroughs.