Description
Synopsys is hiring a Layout Design, Staff Engineer in Noida, India, to design and own custom SRAM, register-file, ROM, and memory compiler IP layouts from floorplan through signoff. The role owns DRC, LVS, ERC, antenna, density, and reliability checks; leads technology-node migrations; collaborates with circuit and CAD teams; develops Tcl, Perl, or Python automation; reviews junior engineers; and supports customer-specific memory customization projects. The position requires a bachelor's or master's degree in a relevant technical field and 8 to 10 years of custom memory layout experience, with Cadence Virtuoso, CMOS, FinFET, and physical verification expertise.
