Description
Synopsys is hiring a Staff IC Layout Engineer to design and optimize custom layouts for embedded memory IPs, standard cells, and IO structures. The role uses Cadence Virtuoso, Synopsys Custom Compiler, and Calibre DRC/LVS tools; it involves optimizing layouts for density, performance, power, and manufacturability, debugging physical design violations, developing layout methodologies and automation flows, and collaborating with circuit and verification teams. The position is based in Ho Chi Minh City and requires a bachelor's or master's degree in a relevant engineering or science field plus at least five years of custom IC layout experience.
