Description
Synopsys is hiring a Layout Design Engineer (Memory) to design custom memory leafcells and standard-cell layouts using Custom Compiler, perform DRC, LVS, and ERC verification, collaborate with circuit and verification engineers, automate layout and verification tasks with Perl, Shell, or TCL, and optimize layouts for performance, area, and power. The role requires at least two years of custom layout experience, familiarity with FinFET technology, proficiency with Custom Compiler and ICV, and a bachelor's or master's degree in a relevant engineering field. The posting lists Da Nang, Vietnam as the city, but the team is described as being in Ho Chi Minh City.
