Description
Micron Technology is hiring a Layout Engineer to build block-level layouts in Cadence Virtuoso, including floorplanning, placement, routing, and optimization. The role applies physical design constraints, ensures DRC, LVS, density, and reliability compliance, supports parasitic extraction and post-layout verification, and creates partial custom layouts for device-level or small analog blocks. Candidates need physical layout experience with Cadence Virtuoso or similar tools, familiarity with physical verification and reliability checks, and the ability to coordinate layout goals with cross-site teams; DRAM, memory-circuit, hierarchical, parasitic-extraction, and custom-layout experience are preferred.
