Description
The Lead Design Engineer will own end-to-end RTL design and integration of SoC, subsystem, and IP blocks, translating architecture into micro-architecture and implementation plans. The role covers Verilog/SystemVerilog development, block and subsystem integration, design quality reviews, debugging, cross-functional collaboration with verification, physical design, DFT, firmware, and architecture teams, and mentorship of junior engineers. The position requires a bachelor’s or master’s degree in a relevant engineering field and 10 to 14 years of digital design experience, with strong RTL, micro-architecture, SoC, IP, and digital design expertise.
