Description
The Digital Design Engineer will understand the DFT architecture of a design and provide scan-insertion collateral to the implementation team to enable scan flows during synthesis. The role requires proficiency with Mentor Tessent, Synopsys DFT Compiler, and Cadence Encounter Test, contribution to ATPG at partition and SoC levels, experience with DFT GLS simulation tools and fault-modeling and coverage-analysis methodologies, familiarity with IEEE 1149.1 (JTAG) and IEEE 1687 (IJTAG), and effective communication and teamwork skills.
