Description
NXP is seeking an experienced DFT Lead Engineer to lead end-to-end design-for-test implementation and signoff for complex SoC/ASIC designs. The role covers RTL integration, full-scan insertion and compression, ATPG, MBIST, LBIST, JTAG, testability analysis, low-power DFT, and silicon debug, while coordinating with design, physical design, verification, and post-silicon teams. Candidates should have a B.Tech or M.Tech in electronics, electrical, or a related field and 5–8 years of core DFT experience.
