Description
Astera Labs is hiring a Lead Emulation Engineer to lead the deployment and execution of complex SoC/IP verification on hardware emulation platforms. The role owns emulation strategy, environment development, RTL bring-up, verification plans, transactors and monitors, automation, performance and stress testing, debugging, and silicon bring-up support, while mentoring engineers and leading technical discussions with design, firmware, architecture, and verification teams. The position requires 6–10 years of experience, strong ASIC/SoC emulation expertise, RTL and digital design knowledge, SystemVerilog/Verilog, UVM, and scripting experience.
