Description
The Senior Physical Design Engineer will lead RTL-to-GDSII physical design for low-power SoCs on advanced 5nm/3nm nodes, covering synthesis, floorplanning, placement, CTS, routing, timing closure, UPF, SoC/SS integration, and signoff. The role requires expertise in Synopsys Fusion Compiler, scripting and automation with Tcl, Python, and Shell, and experience mentoring junior engineers. The posting lists 8–14 years of experience in the role description but also states 4–8 years of hands-on physical design experience in the qualifications, with a pay range of $130,000–$140,000 and benefits including health, dental, and vision insurance.
