Description
Quest Global is seeking an experienced Lead Engineer – Physical Design to lead ASIC/SoC physical design from netlist through GDSII. The role covers floorplanning, power planning, placement, clock tree synthesis, routing, timing closure, power and power-integrity optimization, physical verification support, ECO implementation, tapeout readiness, foundry compliance, automation, and mentorship. The position requires extensive experience with SoC implementation, timing closure, low-power design methodologies, and advanced-node physical design challenges.
