Description
The role is responsible for end-to-end IC verification and signoff from RTL or netlist through GDSII, including synthesis, place-and-route, CTS, timing analysis, physical verification, formal equivalence, custom clocking, routing, ECOs, and flow tuning. It requires hands-on experience with 3nm or smaller technologies, Cadence Innovus, ICV, Primetime, Formality, Fusion Compiler, and scripting in Tcl or Perl, with familiarity with power, IR-drop, EM, and Redhawk.
