Description
NXP is hiring a Senior Design Verification Engineer in Pune to perform hands-on SoC- and IP-level verification for complex ARM-based microcontroller designs. The role owns verification plans and suites, develops UVM environments and tests, creates stimulus and assertions, runs RTL, netlist, gate-level, power-aware, FPGA, and emulation simulations, analyzes coverage, drives verification closure, improves reusable flows, mentors junior engineers, and collaborates with design teams through sign-off. Candidates need 5–12 years of SoC/IP verification experience including successful SoC tape-outs, proficiency in Verilog, SystemVerilog, UVM, constrained-random verification, EDA simulators, assertions, functional coverage, and preferably low-power, interface, memory, security, and analog IP verification knowledge.
