Lead FPGA IP Designer at Lattice

Type: Full-time
Level: Lead
Posted: Jan 28, 2026

Description

Lattice is seeking a highly experienced engineer to join their team in Penang, Malaysia. This role involves leading the research, design, and development of Lattice Foundation IP and FPGA primitives, refining product life cycle processes, and playing a crucial role in coordinating the release cycle of Lattice Foundation IP. The ideal candidate will possess strong communication skills, knowledge of FPGA architecture and software tools, and hands-on experience in complex FPGA RTL design, testbench development, logic verification, and debugging.

Required Skills

FPGA Architecture
RTL Design
Testbench Development
Logic Verification
Timing Closure

Additional Information

Minimum Education: Bachelors, Masters or better in Computer Science, Computer Engineering, Electrical Engineering, or related fields
Required Previous Experiences: 12+ years of experience in FPGA IP and/or EDA tools development
Preferred Qualifications: Expert in multi-domain FPGA primitives such as embedded block RAM, DSP blocks, PLL, oscillators, I/O Gearing, configuration/security or power related silicon features.
Experience in safety related SoC and/or FPGA Soft IP development and verification with proven ability to generate audit ready Functional Safety evidence in compliance with IEC 61508, ISO 26262 or other safety standards.

About Lattice

Lattice

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