Description
Astera Labs is hiring a Lead Logic Design Engineer – UALink IP/Subsystem to lead RTL and microarchitecture development for UALink-based IP and subsystems. The role focuses on high-bandwidth, low-latency data movement and scalable interconnect design, including control and data-path logic, buffering, arbitration, flow control, ordering, error handling, performance and power optimization, and collaboration with verification, SoC integration, and physical design teams. The engineer will also debug complex issues, support silicon debugging, review RTL, and mentor engineers.
