Description
Astera Labs is seeking a Lead Logic Design Engineer to lead the architecture, RTL implementation, integration, and silicon bring-up of complex connectivity IP and subsystems. The role involves translating system requirements into hardware architecture, developing high-performance logic, optimizing performance and power, collaborating with verification and SoC teams, leading technical reviews and mentoring engineers, and supporting post-silicon debugging. Required expertise includes complex connectivity technologies such as PCIe, UALink, Ethernet, CXL, and UCIe, along with SystemVerilog/Verilog, high-speed data paths, and hardware design flows.
