Description
The role translates system-level requirements into hardware block specifications and performs digital design and RTL coding for high-speed data paths and control blocks. It collaborates with verification and physical design teams, reviews test plans, and requires expertise in high-speed datapath design, protocols such as USB3.2, Display Port, MIPI, or Ethernet, RTL-to-GDS flows, low-power design, synthesis, DFT, P&R, timing, and RTL-level power estimation. The posting also requires at least seven years of high-speed datapath design experience, Verilog or SystemVerilog, and a bachelor's or master's degree in electronics engineering.
