Description
Lattice is seeking a Lead Modeling Design Engineer to oversee and contribute to the creation and validation of models for Lattice FPGAs. The role involves leading technical development, collaborating with cross-functional teams, and driving the design and development of high-quality models. Key responsibilities include developing and validating models for various circuits, utilizing simulation tools like Verilog, VHDL, or SystemVerilog, providing technical leadership, analyzing simulation results, optimizing models, documenting processes, and staying updated on advancements in circuit modeling.
